低存储可线性编码的QC-LDPC码设计

QC-LDPC code design with low hardware storage and linear encoding

为了解决构造任意长度、无小停止集且无短环QC-LDPC码的设计问题,研究了基于Tanner图的停止集、围长和最小码重三者之间的关系,提出了QC-LDPC码无短停止距离且无短环的充要条件.在此基础上,为了进一步降低编码复杂度并保留结构化特性,提出了一种具有线性编码复杂度的基于后向迭代的QC-LDPC码.仿真结果表明:所构造的QC-LDPC码的纠错性能与IEEE 802.11n中QC-LDPC码相近,与IEEE 802.16e中QC-LDPC码相比,在误码率为10^(-6)时,可获得0.15 d B的性能增益;此外,该码字只需存储移位因子和单位子矩阵的阶数,所占硬件存储空间明显小于另外2种QC-LDPC码.

To solve the design problem of constructing quasi-cyclic low-density parity-check(QCLDPC)codes of any length without small stopping sets or small girth,the relationship among the stopping set,the girth and the minimum weight based on the Tanner graph is investigated.The necessary and sufficient conditions of the QC-LDPC codes without small stopping sets or small girth are proposed.To further reduce the encoding complexity and maintain the structural characteristics,the backward iteration based QC-LDPC code with linear encoding complexity is proposed.The simulation results show that the error correction performance of the constructed QC-LDPC code is similar to that of the QC-LDPC code in IEEE802.lln.And the designed code achieves a performance gain of0.15dB at the bit error rate of10~6compared with the QC-LDPC code in IEEE802.16e.Meanwhile,the proposed code only needs to store the shift factor and the order of the unit sub-matrix,inducing that the hardware storage resource is obviously smaller than those of the other two QC-LDPC codes.