基于55nm平台的DDR存储器高速I/O电路的设计研究

High Speed I/O Circuit Design of DDR Memory Based on 55 nm Platform

基于55 nm平台,自主设计DDR存储器的高速I/O电路,设计符合ONFI 3.2协议,满足DDR2的设计参数,且兼容SDR和DDR1。本设计的仿真验证结果,符合高速I/O设计应用要求。高速设计的难点在于,在设计之初就要考虑到差分信号的匹配及寄生参数影响的消除,设计经过电路和版图的反复研究修改,最终成功实现设计目标,能够满足高速DDR存储器的I/O接口支持。

The paper describes circuit design,architecture study of high speed I/O in DDR memory based on55nm platform.This design accords with ONFI3.2protocol,meets DDR2parameters and can also work as SDR and DDR1.Besides,simulation validation results are also metioned in the thesis,which satisfies high speed I/O application requirments.The difficulty lies in the design of high speed.It is necessary to eliminate the parasitic effects and consider matching the differential signal at the beginning of the design,the circuit and layout after repeated modifications,to achieve the ultimate success of the design goals,and to meet the I/O interface support for high speed DDR memory.