基于Verilog HDL的功率开关器件控制信号死区时间设置

Power switch device control signal's dead zone time setting based on Verilog HDL

针对高开关频率下多开关管控制信号逆变电路,利用传统模拟电路产生含统一死区时间的控制信号难度大、存在电路安全隐患等问题,提出由单个现场可编程门阵列(FPGA)芯片产生各路含有死区时间的控制信号.首先分析了死区时间效应对输出电压的影响,指出采用传统PWM控制芯片引起死区时间不统一的问题;然后提出了基于Verilog HDL的死区时间设置方法,并给出解决此类问题的通用方法;最后在Modelsim环境下搭建仿真实验平台,实验结果验证了本文所提出方法的可行性.

As for the high switching frequency of multi-switch control signal inverter circuit,it is difficult to use traditional analog circuits to produce control signal with a unified dead zone time and there also exists hidden danger for circuit security.To solve the problems this paper proposes generating the control signal of each channel with a dead zone time by using single field programmable gate array(FPGA)chips.Firstly,the paper analyzes the influence of the dead time effect on the output voltage,and points out the problem of dead time disunity due to the use of traditional PWM control chips.And then the paper presents a dead time setting method based on Verilog HDL,and offers the general solutions.Finally the simulation experiment platform is built under Modelsim environment.The experimental results verify the feasibility of the proposed method.