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PXIe总线可重构测试仪器设计 被引量:7

Design of the PXIe Bus Reconfigurable Test Instrument
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摘要 对传统的通用自动测试系统以及基于现场可编程门阵列的可重构仪器的工作原理和框架结构进行了研究。针对当前传统通用自动测试系统体积庞大、矩阵开关多、易造成仪器损坏、测试效率低等缺点,以通用自动测试系统和可重构仪器的设计理念为基础,提出了一种PXIe总线可重构仪器方案。该仪器采用"核心块+功能块"的框架结构,以现场可编程门阵列组成的可重配置结构为核心,采用AS配置方式,通过PXIe总线实现测试仪器与PC机的通信,设计了数字万用表、信号发生器及频率计等功能模块。利用SOPC Builder创建Nios II处理器系统,设计了配置选择器,实现了各个功能模块的集成、选择及切换。该仪器有效简化了系统结构,减小了仪器接口的冗余度以及开关数量,降低了测试成本,提高了测试效率,同时也使得操作更加灵活和方便。 The operational principles and frame structures of traditional automatic test systems and FPGA-based reconfigurable instruments are researched.To solve the shortcomings of currently common used automatic test systems,such as the huge volume,large amount of matrix switches,easily occurred short circuit and low test efficiency,on the basis of the concept of the general automatic test system and reconfigurable instrument,a scheme of the reconfigurable instrumen based on PXIe bus standard is proposed.In the instrum ent,the“core module+function module”structure is used,with the reconfigurable structure consisting of field programmable gate array as the core,and the AS configuration mode is adopted;the communication between instrument and PC is realized by PXIe bus.In addition,some functional modules are designed,such as the DMM,signal generator and the frequency meter,etc.A Nios II processor system is built by SOPC Builder to integrate these functional modules,and a configuration selector is designed to achieve the integration,selection and switchover of various function modules.This instrument effectively simplifies the system structure,reduces the redundancy of interfaces and the number of switches,as well as improves the test efficiency,decreases the test cost and offers more flexible operation.
作者 苟铭泽 崔少辉 GOU Mingze;CUI Shaohui(Missile Engineering Department,PLA Army Engineering University, Shijiazhuang 050003,China)
出处 《自动化仪表》 CAS 2017年第11期68-70,74,共4页 Process Automation Instrumentation
关键词 自动测试系统 可重构仪器 PXIe总线 现场可编程门阵列 NIOSII处理器 Automatic test system Reconfigurable instrument PXIe bus Field programmable gate array Nios II processor
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