一种具有新型延时单元的鉴频鉴相器设计

Design of phase frequency detector with a novel delay unit

鉴频鉴相器是电荷泵锁相环的关键模块。死区表征鉴频鉴相器对两个输入信号最小相位差的鉴别能力,会使锁相环的杂散特性恶化,是鉴频鉴相器主要的设计考虑之一。基于TSMC 0.18μm RF CMOS工艺,设计了一款具有新型延时单元的无死区鉴频鉴相器。该延时单元基于传输门及反相器设计,利用3位数字控制,实现8种不同的复位延时,可灵活配置,有效消除死区。其具备占用面积小、结构简单、易扩展和易移植等特点。仿真结果表明,设计的鉴频鉴相器具备消除死区的能力,能够应用于锁相环电路。

Phase frequency detector(PFD)is the key module of charge pump phase locked Loops(CPPLL).Dead zone which is one of the primary design considerations of PFD shows the capability of detecting the minimum phase error of the two input signals and it deteriorates the spurious performance of CPPLLs.A no dead zone PFD with a novel delay unit is designed based on TSMC 0.18μm RF CMOS technology.A delay unit composed of transmission gates and an inverters achieving eight different delay time by three control bits is proposed,which can be flexibly configured and effectively eliminates dead zone.It is simple structure with advantages of small area,easy scalability and portability.The simulation results indicate the presented PFD can be applied to PLLs for eliminating dead zone.