LV/HV Twin-Well BiCMOS[B]芯片与制程结构

Structure of LV/HV Twin-Well BiCMOS[B] Chip and Process

LV/HV Twin-Well BiCMOS[B]技术能够实现低压5 V与高压100~700 V(或更高)兼容的BiCMOS工艺。为了便于高低压MOS器件兼容集成,采用具有漂移区的偏置栅结构的HVMOS器件。改变漂移区的长度,宽度,结深度以及掺杂浓度等可以得到高电压。采用MOS集成电路芯片结构设计﹑工艺与制造技术,依该技术得到了芯片制程结构。

LV/HV Twin-Well BiCMOS[B]technology can achieve a low voltage 5 V and a high voltage 100~700 V(or higher)compatible BiCMOS process.In order to facilitate the compatibility and integration of high and low voltage MOS devices,a HV MOS device with bias grid structure with drift region is used.High voltage can be obtained by changing the length,width,depth,and doping concentration of the drift region.Using MOS integrated circuit chip structure design,technology and manufacturing technology,the chip process structure is obtained by this technology.