低相位噪声和低参考杂散CMOS锁相环的优化设计与实现

Optimization Design and Implement of Low Phase Noise and Low Reference-Spu CMOS Phased-locked Loop

基于Simulink建立的CMOS电荷泵锁相环的动态模型,对电荷泵锁相环的环路参数与环路稳定性的关系进行了仿真与分析,根据分析结果确定了4 GHz锁相环的环路参数,并围绕低相位噪声和低参考杂散设计了锁相环各单元电路结构。该锁相环采用SMIC 0.18μm CMOS工艺进行了流片,芯片面积为675μm×700μm。测试的VCO在控制电压为0.3 V^1.5 V时,振荡频率为3.98 GHz^4.3 GHz;当分频比为1036,参考信号频率为4 MHz,锁定状态下锁相环的相位噪声测量值为-120.5d Bc/Hz@100 k Hz及-127.5 d Bc/Hz@1 MHz;电路参考杂散约为-70 d B,整体性能优良。

According to the established dynamic model of CMOS charge pump PLL(phased-locked loop)based on the Simulink,the simulation and analysis of the loop stability with the change of the main loop parameters have been finished,the loop parameters of 4GHz PLL are determined,and the circuit structures of the PLL are designed for the low phase noise and low reference spur based on the analysis.The PLL is implemented in the 0.18μm CMOS technology of SMIC.The chip area is 675μm×700μm.The measured frequency of the VCO is from 3.98 GHz to 4.3 GHz when the control voltage is changed from 0.3 V to 1.5 V,the measured phase noise of the PLL under locked is-120.5 dBc/Hz@100 kHz and-127.5 dBc/Hz@1 MHz when the frequency dividing ratio is 1036 and the reference frequency is 4 MHz.Reference-spu is about-70 dB,the testing performance of the chip is excellent.