基于延迟锁相环和锁频环结构的全数字同步倍频器

All-Digital Synchronous Frequency Multiplier Based on Delay-Locked Loops and Frequency-Locked Loops

针对现有基于PLLs/DLLs的全数字化同步倍频器结构存在的不足,提出了一种基于双环结构的全数字同步倍频器。它由延迟锁相环和锁频环共享一个共同的参考时钟信号(F_(REF))构成,不需要任何模拟组件,采用Verilog-HDL语言设计,在Altera DE2-70开发板上实现合成;实验结果表明,所提出的结构相比于现有的结构,能够获得更高频率的输出时钟信号,提供更好的频率分辨率、更好的抖动性能和高倍乘因子。

Aiming at the shortages of existing all-digital synchronous multiplier structure based on PLLs/DLLs,an all-digital synchronous multiplier based on a dual-loop architecture is proposed.It is composed of proposed delay-locked loops and frequency-locked loops that share a common reference clock signal(F REF)and requires no any analog components.The proposed architecture is designed using the Verilog-HDL language and synthesized on the Altera DE2-70 development board.The experimental results show that the proposed architecture,compared with the existing architectures,can generate output clock signal having a higher frequency,provide better frequency resolution and jitter performance as well as high multiplication factor.