基于FPGA实现TDC的布局布线优化方法研究

Optimization of digital TDC circuit routing based on FPGA

时间数字转换器TDC,作为一种高分辨率的时间间隔测量设备,广泛应用于现代电子系统。基于可编程逻辑门阵列FPGA实现时间数字转换器,具有灵活稳定、高速度、低成本的特点,成为了目前研制时间间隔测量计数器的热门方案。采用该方法实现时间数字转换器,其设计分辨率是由内部的加法进位链决定的。如何对FPGA中实现的加法进位链的布局布线进行优化,就成为决定时间数字转换器设计分辨率的关键问题。文章采用阿尔特拉(Altera)公司的FPGA器件实现时间数字转换器,使用Quartus II软件进行布局布线设计,并针对上述问题在开发过程中提出解决方法。同时根据Quartus II开发软件的不同版本,分别提出相应软件的布局布线优化方法。测试表明,通过对进位链的布局布线进行优化可以实现100.3 ps测量分辨率的时间数字转换器。

As a high-resolution time interval measurement equipment,time-to-digital converter(TDC)is widely used in modern electronic system.The time and digital converter based on programmable logic gate array(FPGA)is of flexible,stable,high speed,low cost characteristics,which has become popular method in development of time interval measurement counter nowadays.The resolution of the time-to-digital converter designed by this method is determined by the internal addition of the carry chain.How to optimize the layout and routing of the carry chain in FPGA is the key problem to realize the resolution of time-to-digital converter.The article used Altera’s FPGA component to implement TDC and Quartus II software to do layout and routing,and proposed solutions to the above problems in the process of development.At the same time,according to different versions of Quartus II development software,the corresponding software layout and routing optimization method are proposed respectively.Tests show that the time-to-digital converter implemented by optimizing the layout and routing of the carry chain can realize a 100.3 ps measurement resolution.