基于FPGA的粗粒度可重构系统拓扑网络结构开发

Network Topology Exploration of Coarse-Grained Reconfigurable Architecture Based on FPGA

针对粗粒度可重构系统架构的应用开发,本文提出了一个基于FPGA的粗粒度可重构系统架构验证平台及相应的互连拓扑网络结构开发流程.基于FPGA开发板,构建粗粒度可重构系统的验证模块及模块之间的拓扑互连被自动插入从而生成该系统架构的硬件验证平台.针对不同的应用,该平台可以根据拓扑开发流程对不同拓扑互连策略下粗粒度可重构系统架构的性能和功耗进行评估分析.大量实验表明:CGRA的互连网络对该系统架构的性能和功耗有着巨大的影响,最适宜的粗粒度可重构体系架构的互连策略取决于所选的拓扑结构.根据评估所获得的系统性能、功耗以及FPGA资源占用率,设计者可以在较短的开发时间内准确地确定该应用最适宜的粗粒度可重构系统的拓扑互连策略.

With regard to the application development of coarse-grained reconfigurable architecture,a CGRA emulation platform based on FPGA and an exploration flow of network topology were presented in this paper.Based on FPGA,IP blocks(emulation blocks)and topology interconnection between IPs were inserted automatically to generate a CGRA hardware emulation platform.Following the exploration flow,the platform was used to evaluate timing performance and energy consumption of the CGRA with different topologies for different applications.The experiments demonstrate that the interconnection network of CGRA has a huge impact on timing performance and energy consumption,and the most appropriate interconnection strategy of CGRA strongly depends on the selected topology.Depending on the timing performance and energy consumption results obtained and the occupancy rate of FPGA resources,the designer can select the appropriate interconnection strategy of CGRA in a short exploration time and with precision.