高速ADC中具有失调对消的采样保持电路设计

Circuit Design of Offset Canceling Sample-and-hold Architecture for High-speed ADC

基于采样速率最快的全并行(Flash)ADC(Analog to Digital Converter)结构,采用UMC 0.18 um CMOS工艺,设计了一种具有失调对消的采样保持电路(Track-and-Hold Circuit)。该THC嵌入比较器的两级预放大电路之中,不仅可以简化ADC结构,还进一步提高了比较器速度。通过电路工作相位ф_1,ф_2交替变换,不同相位的失调分量等值反向,输出累加实现对比较器失调对消。最后,在2 GHz时钟频率下进行仿真,仿真结果表明,输入信号为800MHz时,具有失调对消THC的Flash ADC较传统结构的SFDR(Spurious Free Dynamic Range),SINAD(Signal to Noise And Distortion)分别提高了8.26 dB、3.14 dB,ENOB(Effective Number Of Bits)提高了0.52 bits。

Based on the fastest Flash ADC architecture,an offset cancellation Track-and-Hold Circuit(THC)applying UMC 0.18um CMOS process is implemented.The proposed THC is embedded in two stage preamplifiers of comparator,which can not only simplify structure of ADC,but also further improve the speed of comparators.Moreover,by alternately changing circuit phase?准1,?准2,offset values would be canceled by the accumulation of output values,as offset values are equivalent but reverse in different phase.Finally,the Flash ADC with proposed THC and the conventional Flash ADC are simulated under 2 GHz clock frequencies respectively.Simulation results show that SFDR and SINAD of proposed ADC can be improved by 8.26 dB and 3.14 dB respectively compared to traditional one in 800 MHz input frequencies.The ENOB can also be improved by 0.52 bits.