基于混合三模冗余的容忍双点翻转锁存器

Double Node Upset Tolerant Latch Based on Hybrid TMR

随着集成电路工艺的飞速发展,电路内部节点对于高能粒子入射的敏感性急速增大,锁存器中辐射效应引起的软错误急剧增多.进入90 nm工艺以后,电荷共享导致的双点翻转已经成为影响可靠性的严重问题.为此,基于混合三模冗余机制,提出2种加固锁存器结构:TMR-2D1R锁存器和TMR-1D2R锁存器.传统的三模冗余锁存器包括3个同构的D-latch和1个表决器;TMR-2D1R锁存器包括2个D-latch,1个RHM单元和1个表决器,可以部分容忍双点翻转;TMR-1D2R锁存器包括1个D-latch,2个RHM单元和1个表决器,可以完全容忍双点翻转.与相关加固锁存器进行比较的结果表明,TMR-1D2R锁存器在延迟、功耗、面积和加固性能等方面取得了较好的折中.

With the continuous development of technology,internal nodes of integrated circuits are more sensitive to high energy particle striking,and radiation induced soft error in latch increases quickly.Research shows that double node upset caused by charge sharing is becoming a serious reliability issue under 90nm technology.This paper presented two hardening latches:TMR-2D1R latch and TMR-1D2R latch,which are based on hybrid TMR mechanism.Traditional TMR latch comprises three D-latches and one voter.TMR-2D1R latch comprises two D-latches,one RHM and one voter.TMR-2D1R can partially tolerate single event double node upset.TMR-1D2R latch comprises one D-latch,two RHMs and one voter.TMR-1D2R latch can totally tolerate single event double node upset.Compared with other hardening latches,the proposed latch make better tradeoff in terms of delay,power consumption,area and hardening performance.