基于埋容材料的PDN阻抗仿真与优化

Simulation and Optimization of PDN Impedance based on Embedded Capacitance Material

为满足高速、高密PCB对电源完整性的要求,降低电源分配网络(PDN)阻抗,减少去耦电容数量,对分立电容、电源/地平面、埋容材料等影响PDN阻抗的因素进行分析,利用Cadence Sigrity软件对埋容材料在降低PDN阻抗方面的作用进行仿真,优化去耦电容。结果表明,埋容材料的高介电常数、薄介质厚度的特性可减小分立电容的安装电感,降低分立电容与电源/地平面的反谐振,在优化PDN阻抗与减少去耦电容方面作用显著,非常适用于高密板及对电源质量要求较高的场合。

In order to meet the requirements of high-speed and high-density PCB for power integrity,decrease PDN(Power Distribution Network)impedance and reduce the number of decoupling capacitors,the factors affecting the impedance of PDN such as discrete capacitance,power/ground plane and embedded capacitance material are analyzed.Simulation with Cadence Sigrity software is done on the effect of embedded material in reducing the PDN impedance,and the decoupling capacitor also optimized.The simulation results indicate that the embedded material could,for its characteristics of high dielectric constant and thin medium thickness,reduce the mounting inductance of discrete capacitor,decrease the parallel resonance of discrete capacitor and the power/ground plane,and exhibits significant roles in the optimization of PDN impedance and the reduction of decoupling-capacitor number.And thus it is very suitable for highdensity PCB and for the occasions with high requirements for power supply.