一种基于CS32F0XX芯片的ADC测试结构的优化方法及其FPGA实现

An Optimization Method of ADC Test Structure Based on CS32F0XX Chip and its FPGA Implementation

随着超深亚微米工艺的发展和So C基于IP核的设计,使芯片逻辑功能越来越复杂,需要更多的引脚和测试资源。为了满足不同客户的需求,要求芯片的引脚数有灵活性,这直接导致了对芯片测试资源使用有所限制。使用较少的硬件资源,完成复杂的逻辑功能测试,是芯片测试逻辑设计的核心技术之一。主要介绍对ADC所需的测试资源的优化,首先介绍了传统ADC测试结构及其局限性,然后介绍了ADC优化后的测试结构,使之能够在较少芯片引脚资源的条件下保证测试灵活性。在此基础之上,搭建了ADC数模仿真环境,并使用NC-SIM软件对ADC基本功能进行了仿真测试。

With the development of ultra deep submicron technology and the design of SoC based on IP core,the logic function of the chip is becoming more and more complex,and more pins and testing resources are needed.In order to meet the needs of different customers,the pin number of the chip is flexible,which directly leads to the limitation on the use of the chip test resources.The use of less hardware resources to complete the complex logic function testis one of the core technologies of the logic design of the chip test.This paper mainly introduces the optimization of test resources for ADC.First,the traditional ADCtest structure and its limitations are introduced.Then,the test structure after ADCoptimization is introduced,so that it can ensure test flexibility under the condition of fewer chip pins.Finally,on this basis,the ADC digital analog simulation environment is built,and the basic functions of ADCare simulated and tested byusingNC-SIMsoftware.