降低数字集成电路测试功耗的向量排序方法

A vector sorting method for reducing test power consumption in digital integrated circuits

分析研究测试数字集成电路期间产生的功耗问题,在此基础之上提出新的测试向量排序方式,希望能够将测试期间电路的翻转次数减低。按照测试特征以及电路结构等可以使该方法对输入影响度系数进行计算,在对故障覆盖率不产生影响的基础之上对测试功效进行降低处理。通过试验可以看出,该种方式在实际测试期间能够至少降低47.24%的功耗,可以在测试中推广使用。

Based on the analysis and research of the power consumption problems during the test of digital integrated circuits,a new sorting method of test vectors is proposed,hoping to reduce the number of turns in the test period.According to the test characteristics and circuit structure,the method can calculate the input influence coefficient and reduce the test efficiency based on the failure coverage.It can be seen from the test that this method can reduce the power consumption by at least 47.24%during the actual test,and can be used in the test.