基于FPGA的多节点电力线信道仿真器的设计与实现

Design and implementation of multi-node power line channel emulator based on FPGA

电力线信道仿真器的研发能够避免大量重复、耗时的场外测试实验,能够节省大量的人力物力,缩短研发周期,加快电力线通信技术的发展。基于SystemGenerator平台设计了多节点的低压宽带电力线信道仿真器并通过FPGA进行了实现。该信道仿真器包括AD采样模块、信号处理模块以及DA输出模块,能够对电力线网络中多个节点间的信道进行模拟,同时能够满足信道双向通信的需求。通过理论数据与实测数据的对比分析,结果表明该电力线信道仿真器能够根据实际电力线场景对相应的宽带电力线信道衰落进行模拟。

The research of power line channel emulator can help researchers to avoid a large number of repeated and time-consuming outdoor test experiments,save a lot of manpower and resources,shorten the development cycle,and speed up the development of power line communication technology.This paper,based on the System Generator platform,designs a multi-node low-voltage broadband power line channel simulator and implements it through FPGA.The channel emulator includes AD sampling module,signal processing module and DA output module,which can emulate the channel between multi-nodes in the power line network and meet the needs of two-way communication of the channel.Through the comparison between the theoretical data and the measured data,the results show that the power line channel emulator can emulate the corresponding broadband power line channel fading according to the actual power line scene.