高速率低延时Viterbi译码器的设计与实现

Design of high-speed and low-latency Viterbi decoder

在Vitebi译码器的实现中,由于路径存储方式的不同分为回溯和寄存器交换模式,效果是延时与资源消耗一般只能二取其一,互为矛盾。采取3~6长度的RE-寄存器交换,混合回溯模式,极大地减少了回溯时间,并减少了路径存储空间需求,付出的代价是每ACS增加2~5 LUT;再结合其他Viterbi译码器优化算法,如分支度量一次计算,每ACS查找——即4选1等措施,实现了高吞吐量(340 Mb/s)、低延时、低资源消耗的全并行Viterbi译码器。

In a Viterbi decoder,there are two known memory organization techniques for the storage of survivor sequences,namely register exchange method and traceback method.This paper presents a new survivor path storage scheme that enables short latency in area-efficient Viterbi decoder.This is achieved by introducing part register exchange method into traditional traceback method.Since more path information is read per clock,the traceback time is largely shortened,and the path memory size is also saved greatly.On contrast to conventional register exchange and traceback method,the new method has obvious advantage of hign speed,low resource cost and low-latency.