基于Vivado HLS的Canny算法实时加速设计

Real-time acceleration design of Canny algorithm based on Vivado HLS

针对Canny边缘检测算法在实时图像处理过程中运算耗时长、数据运算量大的缺点,研究了利用Vivado HLS实现Canny边缘检测算法的硬件加速方法。该方法由FPGA的逻辑资源生成算法对应的RTL级硬件电路,实现算法硬件加速。实验结果表明,该方法能快速实时检测图像边缘,有效降低FPGA设计图像算法的难度,可以应用到实时视频图像处理中。

On the shortcomings of Canny edge detection algorithm in the real-time image processing time-consuming and large amount of data for computation,the hardware acceleration method of Canny edge detection algorithm using Vivado HLS is proposed.The method,implemented hardware acceleration,generates the RTL level hardware circuit corresponding to the algorithm of the FPGA logic resources.The results show that the method can quickly detect the edge of the image and effectively reduce the difficulty of FPGA design image algorithm,which can be applied to the real-time video image processing.