摘要
在遥测系统中,LVDS接口有着传输速度高的优点,想保证数据传输的高效性与稳定性,必须确保LVDS传输链路的可靠性。在此次设计中,通过在硬件电路中增加阻抗匹配和均衡加重技术来提高电路的可靠性。在逻辑设计中,通过采用bit9和bit8标志位来区分有、无效数据与3路数字信号的方法来消除失锁现象,从而提高数据传输的稳定性。经验证,系统实现了以300 Mbit/s的速率在30 m屏蔽电缆中传输数据,误码率为零,提高了LVDS传输链路的可靠性与稳定性。
In the telemetry system,the LVDS has the advantage of high transmission speed,if you want to ensure the efficiency and stability of data transmission,the reliability of an LVDS transmission link must be ensured.In this design,the reliability of the circuit is improved by increasing the impedance matching and the balanced weighting technology in the hardware circuit.In the logical design,the stability of data transmission is improved by using bit9 and bit8 marker bits to distinguish valid data,invalid data and the 3-way digital signal.Through this scheme design,the system realizes the transmission data of 300 Mbit/s at 30 meters of shielding cable,the error rate is zero,and the reliability and stability of LVDS transmission link are improved.
作者
张波
李杰
张海鹏
胡陈君
ZHANG Bo;LI Jie;ZHANG Haipeng;HU Chenjun(Key Laboratory of Instrumentation Science and Dynamic Measurement North University of China,Ministry of Education,Taiyuan 030051,China;Suzhou Fashion Nano Technology Co.,Ltd,Suzhou Jiangsu 215000,China3)
出处
《电子器件》
CAS
北大核心
2018年第5期1237-1241,共5页
Chinese Journal of Electron Devices
基金
国家自然科学基金项目(51575500)
关键词
FPGA
LVDS
阻抗匹配
可靠性
高速传输
FPGA
LVDS
impedance matching
reliability
the high-speed transmission
