基于FPGA的多路并行PCM数据收发模块的设计

Design of Multi-Path Parallel PCM Data Transceiver Module Based on FPGA

在自动测试系统中,为了实现多路并行PCM数据的同时接收与处理,设计了一种以FPGA为主控制核心的并行数据收发模块,该模块实现了隔离RS422接口电路设计,双通道并行PCM数据的接收,隔离分档电压输出等。并行数据收发的逻辑设计,采用乒乓操作的思想轮流通过单通道回传给上位机,由软件对数据进行分包检验处理。经过多次的实际测试验证每路PCM数据的传输速率可达1Mbyte/s,在保证合理性以及可靠性的前提下,相对于单通道数据的传输在速率上有了大幅提高。

In the automatic test system,in order to achieve the multi-channel parallel PCM(Pulse Code Modulation)data receiving and processing at the same time,the design of a control module is given priority with the FPGA parallel data transceiver control core.The module has realized the isolated RS422 interface circuit design,dual channel parallel PCM data receiving,isolation step voltage output,etc.The logic design of parallel data transceiver,by adopting the idea of ping-pong operation through a single channel in turn back to the PC,subcontract inspection by the software for data processing.After several times of actual test to verify each of PCM data transmission rate can be up to 1 Mbyte/s,on the premise of guarantee the rationality and reliability,compared with the single channel data transmission had a sharp increase in the rate.