低功耗自适应偏置无片外电容低压差稳压器

Low-power Adaptively Biased Output-capacitor-free Low-dropout Regulator

设计了一款低功耗自适应偏置无片外电容低压差线性稳压器.为了解决由于设计和工艺中存在不匹配造成每级误差放大器不同类型输入管的反型系数在自适应偏置下变化不同步问题,提出了由循环折叠共源共栅放大器和跨导提高放大器构成的误差放大器结构,同时采用推挽输出结构提高了对功率管的驱动能力.该无片外电容低压差稳压器采用嵌套密勒补偿和自适应偏置,解决了轻负载时的稳定性问题,同时提高了轻负载下的电流效率.芯片采用SMIC 0.18μm CMOS工艺设计,版图面积为0.019 9mm^2.蒙特卡罗后仿真的结果表明,其负载电流范围为10μA～100mA,最大负载寄生电容为100pF,最小负载下静态电流为1μA,负载调整率和电源调整率分别为3.5μV/mA和0.372mV/V.设计的低压差稳压器具有低功耗、无片外电容、面积小的优点,是片上系统中电源管理知识产权核的良好选择.

A low-power adaptively biased output-capacitor-free low-dropout linear regulator was designed.In order to tackle the problem that the inversion coefficients of different types of input transistors in each error amplifier stage may vary asynchronously under adaptive bias caused by mismatches in the design and process,an error amplifier comprised of the recycling folded cascode amplifier and transconductance-boosting amplifier was proposed.The driving ability for the power transistor was improved by the adopted pull-push output structure.Nested Miller compensation and adaptive bias were used to solve the stability problem of output-capacitor-free low-dropout regulator and improve the current efficiency at light loads.The regulator chip was implemented in SMIC 0.18μm CMOS process with a layout area of 0.019 9 mm 2.The Monte Carlo post-simulation results show that the load current range is 10μA^100 mA with the maximum load parasitic capacitance of 100 pF,and the quiescent current is 1μA at the minimum load condition.The load regulation and line regulation are 3.5μV/mA and 0.372 mV/V,respectively.The designed low-dropout regulator has the merits of low power consumption,no off-chip capacitor and small area,which indicates that it is a good choice as intellectual property core of the power management for the system on chip.