摘要
本文叙述的是一个8通道12位SARA/D转换器(ADC)的设计和实现。基于逐次逼近型寄存器(SAR)的体系结构,本A/D转换器有着140KSPS的最大采样率,并且对于一个1.8V的电源来说,其整个ADC仅消耗1mW,其关机电流仅为1uA。低压ADC通过0.18μm2P4MCMOS工艺制作。ADC占用面积为0.3mm×0.35mm。在高性能点(12-bit,140KSPS)时,ADC的INL和DNL分别为0.7LSB和0.66LSB。
Design and realization of an 8-channel 12bit SAR A/D converter(ADC)is described in this pap er.Based on the successive approximation register(SAR)architecture,this A/D Converter has a maxim um sample rate of 140KSPS and the entire ADC consumes only 1mW from a 1.8V supply and the shutdown cu rrent is only 1uA.?The low-power ADC was fabricated by a 0.18mm 2P4M CMOS process.The lay the ADC is 0.3 mm*0.35 mm.At the high performance point(12-DNL of the ADC are 0.7LSB and 0.66LSB,respectively.
作者
刘红兵
Liu Hongbing(Hunan Railway Professional Technology College,Zhuzhou Hunan,412001)
出处
《电子测试》
2018年第20期27-28,68,共3页
Electronic Test
基金
2016年湖南省教育厅科学研究课题"基于超级电容城市轨道交通车辆再生制动能量回馈储能系统的研究"(17C1038)阶段成果