适用于均衡器系统的高速低失调限幅放大器

A Low Offset High Speed Limiting Amplifier for Equalizer System

基于0.13,μmCMOS工艺,设计了一款适用于均衡器系统的高速低失调电压的限幅放大器.电路设计中采用有源负载电感效应技术来提高系统的带宽;同时,为了优化由器件间失配导致的失调电压,提出了一种改进的失调电压消除技术.通过在负反馈环路中使用18,pF的电容来构建低频滤波器,该技术可以实现22.8,kHz的高通截止频率.蒙特卡罗仿真结果表明,该放大器输出端的直流失调电压均值为78.48,μV,标准差为3.73,mV.工作在1.8,V电源电压下,限幅放大器的带宽为6.0,GHz,增益为24.2,dB,功耗为23.6,mW,版图面积为0.030,6,mm2(170,μm×180,μm).

A low offset high speed CMOS differential limiting amplifier was proposed in 0.13,μm CMOS technology for equalizer system.In the design,active load inductive peaking technique was exploited to broaden the system’s bandwidth.Meanwhile,in order to attenuate the offsets coming from mismatch between devices,an improved offset cancellation technology was implemented.With a total capacitor of 18,pF in the negative feedback loop,the design can provide a high-pass cutoff frequency of 22.8,kHz in typical condition.Monte Carlo simulation shows that the design has a low offset voltage of 3.73,mV at 1,sigma on the output of limiting amplifier with a mean value of 78.48,μV.Consuming 23.6,mW from 1.8,V power supply,the design achieves a 6.0,GHz bandwidth and 24.2,dB gain,and the core size of the limiting amplifier is 0.030,6,mm^2(170,μm×180,μm).