超外差式多模数字接收机设计与FPGA实现

Design and FPGA Implementation of a Super Heterodyne Multimode Digital Receiver

为了满足不同通信系统之间灵活切换的要求,设计了一种超外差式多模数字接收机。针对两种传统多模数字中频结构消耗巨大资源的问题,以可定制FPGA处理方式利用牺牲时钟换取资源的思想提出资源优化的动态参数配置多模数字中频结构,节约了50%的资源,结合超外差式射频前端结构完成多模数字接收机的设计。在自主设计的射频与中频板硬件平台上进行的板级测试结果表明,超外差式多模数字接收机能够兼容2G/3G/4G模式。

In order to meet the requirements of flexible switching between different communication systems,a super heterodyne multimode digital receiver is proposed.Aiming at the resource consumption problem of two traditional multimode digital medium frequency structures,a resource optimized medium frequency structure based on the idea of sacrificing the clock for resources by customized FPGA is proposed,which is capable of dynamic parameter configure.Combining medium frequency structure which save 50%resource with the super-heterodyne RF front-end structure,the multimode digital receiver is designed.The board-level experimental results based on the self-designed RF and medium frequency hardware platforms illustrates,the designed super heterodyne multimode digital receiver is compatible with 2G/3G/4G modes.