JESD204B接收系统同步技术研究与实现

Research and Implementation of Synchronization Technology in JESD204B Receiver

针对JESD204B协议规定的接收系统的同步问题,提出了一种针对子类1的四字节并行处理实现方案。将数据流中提取的控制信息与数据信息并行处理,简化了接收系统中各种同步的处理过程,同时将电路工作时钟频率从1.25 GHz降低到312.5 MHz,简化了CMOS实现工艺要求。采用Verilog HDL实现并与XILINX官方IP核进行了对接验证,还在Design Compiler平台采用TSMC 65 nm工艺进行综合,结果表明:该设计方案在功能,工作频率等方面均能够满足JESD204B协议要求。

A quad-byte parallel processing solution for subclass 1 is proposed according to the synchronization system in JESD204B receiver.It is achieved by using a parallel topology which makes control information and user data process respectively,completed a variety of synchronization process,also reduced the clock frequency requirement to 312.5 MHz from 1.25 GHz,which makes it facilitate to implement at a low cost CMOS process.A docking verification between the Verilog model and XLINX official JESD204B 6.1v IP core is performed,the design is also synthesized using TSMC 65nm CMOS process at Design Compiler platform,and results show that it is meet the JESD204B standard specification at function and in the operating frequency.