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SDH E1时隙可配帧格式及数据编码的设计与FPGA实现技术 被引量:2

Design and FPGA implementation technology of SDH E1 slot format and data encode
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摘要 SDH(synchronous digital hierarchy)光纤网络在国防、电力、通信和交通等行业存在广泛的应用,E1通道具有可靠性和稳定性高的特点,可采用E1通道实现整个SDH光纤网络的时间同步。在介绍E1帧格式及HDB3编码原理的基础上,同时兼顾SDH光纤网络数据传输核心业务,设计并实现了时隙可配的SDH E1帧格式,针对传统SDH E1帧格式占用时隙固定、灵活性差等不足,设计了E1可配置时隙的帧格式传输结构,基于FPGA(field programmable gate array)实现了时码信息在E1帧格式31时隙中任意一个时隙的HDB3编码发送,验证了E1可配时隙帧格式生成和HDB3编解码的可行性及正确性。该设计极大增强SDH光纤网络时间同步的灵活性,提高了用户使用的便捷性。 Synchronous digital hierarchy(SDH)optical network is widely applied in national defense,electric power,communication and transportation industries.We can use E1 channel to achieve time synchronization in SDH optical network,because E1 channel has high reliability and high stability.In this paper,based on E1 frame formatting and HDB3coding,considering demands of users,we design and implement the configurable time slot in frame format and data coding.Based on FPGA,the HDB3encoding transmission of time code information in any one of the31time slots of E1 frame format is realized.This design enhances the flexibility of time synchronization in SDH optical fiber network and improves the convenience of users.
作者 池飞 武建锋 何在民 CHI Fei;WU Jian-feng;HE Zai-min(National Time Service Center,Chinese Academy of Sciences,Xi'an 710600,China;Key Laboratory of Precise Positioning and Timing Technology,Chinese Academy of Sciences,Xi'an 710600,China;Key Laboratory of Time and Frequency Primary Standards,Chinese Academy of Sciences,Xi'an 710600,China;School of Electronics,Electrical and Communication Engineering,University of Chinese Academy of Sciences,Beijing101048,China;University of Chinese Academy of Sciences,Beijing 100049,China)
出处 《时间频率学报》 CSCD 2018年第4期317-325,共9页 Journal of Time and Frequency
基金 地理信息工程国家重点实验室资助项目(SKLGIE2016-M-1-3) 中国科学院"西部之光"人才培养计划西部青年学者B类基金资助项目(Y607YR8601)
关键词 SDH E1 可配时隙 数据编码 帧格式 现场可编程门阵列 synchronous digital hierarchy E1 configurable time slot data coding frame format field programmable gate array
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