基于SoC FPGA的高速EDIB总线通信电路设计

Design of High-speed EDIB Communication Circuit Based on SoC FPGA

针对当前石油测井领域普遍采用"DSP+FGPA"、"MCU+FPGA"等双芯片架构实现EDIB总线通信功能时存在的可靠性低、体积大、功耗大的问题,本文提出采用SoC FPGA架构实现该功能,并具体介绍了EDIB总线读写模块、上传数据通道模块以及下载命令通道模块的设计方法。实验结果表明,该设计满足应用要求。

In the current oil well-logging field,the dual-chip architectures such as"DSP+FGPA"and"MCU+FPGA"are widely used to realize the EDIB bus communication function,which has the problems of low reliability,large volume,and large power consumption.The EDIB bus communication function using SoC FPGA architecture is proposed,and specifically introduces the design method of the EDIB bus reading and writing module,the upload data channel module,and the download command channel module.The experiment results show that the design meets the application requirement.