一种超低功耗全CMOS基准电路

An ultra-low powerAll-CMOS current and voltage reference circuit

设计了一种超低功耗全CMOS基准电路:既能产生1 nA的基准电流又能产生560 mV的基准电压。通过亚阈值设计方法有效降低了基准电路的功耗;采用工作在深线性区的MOS管取代了传统基准电路中的电阻,大大降低了面积;采用共源共栅电流镜提高了电源抑制比。利用SMIC 55 nm的工艺,使用Cadence Spectre对电路进行了仿真。仿真结果表明,在-40℃到110℃的温度范围内,基准电流的温漂系数为0.28%/℃,基准电压的温漂系数为24 ppm/℃;在0.9 V到2 V电源电压范围内,基准电流的电源电压调整率为2.6%/V,基准电压的电源电压调整率为0.48%/V;在100 Hz处,基准电流的PRSS为-34 dB,基准电压的PRSS为-50 dB。功耗为6 nW,芯片版图面积仅0.000 42 mm2。

A6nW CMOS current and voltage reference circuit is proposed,which is implemented without resistance and with only standard CMOS transistor.The proposed circuit has an attractive merit:it can afford reference current and reference voltage simultaneously.The sub-threshold region design method is used to decrease the circuit power.The MOSFET worked in deep linear region replaces the passive resistance,and through this way the chip layout area is reduced.The power supply rejection ratio(PSRR)isreduced by the cascode current mirror.The current and voltage reference circuit is designed and simulated in SMIC 55nm CMOS process.The simulation results show that the temperature coefficient of the reference current and reference voltage are 0.28%/℃ and 24ppm/℃in a range of -40℃ to 110℃,and the linear regulation are 2.6%/V and 0.48%/V in supply range of 0.9V to 2V.Also,the PSRR of reference current and voltage are -34dB and -50dB at 100Hz.The power dissipation is only 6nW.The chip layout area is 0.00042mm^2.