基于Qt的Verilog故障注入工具设计与实现

Design and realization of Verilog fault injection tool based on Qt

为方便设计人员验证电子电路的可靠性,设计了基于Qt的Verilog故障注入工具。该工具通过语法语义分析器解析Verilog源文件,获得代码中全部故障注入点;采用故障注入管理器获取用户故障注入参数并传递给底层函数,实现对Verilog工程的故障注入。实验结果表明,该故障注入工具能够根据用户指令对Verilog工程进行故障注入,对电路的容错机制进行可靠分析和评价,对电子电路的容错方案设计有很大帮助。

In order to facilitate designers to verify the reliability of electronic circuits,a Verilog fault injection tool based on Qt is designed.This tool parses Verilog source files through a syntax and semantics analyzer,and obtains all fault injection points in the code.The fault injection manager is used to obtain the user fault injection parameters and transfer them to the underlying function to realize the fault injection of Verilog project.The experimental results show that the fault injection tool can inject the fault into Verilog project according to user's instructions,analyze and evaluate the fault tolerance mechanism of the circuit reliably,which is very helpful to the design of fault tolerance schemes for electronic circuits.