LV/HV Twin-Well BCD[B]技术(1)芯片与制程剖面结构

Structure of LV/HV Twin-Well BCD[B] Chip(1) and Process

LV/HV Twin-Well BCD[B]技术(1)能够实现低压5 V与高压100～700 V (或更高)兼容的BCD工艺。为了便于高低压MOS器件兼容集成,采用源区为硼磷双扩散形成沟道的具有漂移区的偏置栅结构的HV LDMOS器件。改变漂移区的长度,宽度,结深度以及掺杂浓度等可以得到不同的高电压。采用MOS集成电路芯片结构设计﹑工艺与制造技术,依该技术得到了芯片制程结构。

LV/HV Twin-Well BCD[B]technology(1)can realize BCD process compatible with low voltage 5V and high voltage 100-700 V(or higher).In order to facilitate compatible integration of high and low voltage MOS devices,HV LDMOS devices with bias gate structure with drift region and channel formed by double diffusion of boron and phosphorus in source region are adopted.Different high voltage can be obtained by changing the length,width,junction depth and doping concentration of the drift region.The structure design,process and fabrication technology of MOS integrated circuit chip are adopted,and the chip fabrication structure is obtained according to this technology.