一种基于异构计算平台的FPGA动态重配置方法

A FPGA Dynamic Reconfiguration Method Based on Heterogeneous Computing Platform

通过对异构计算技术的研究,该文提出了嵌入式异构计算模型,实际构建了由多类异构处理机作为计算资源并通过串行RapidIO高速交换总线互连的嵌入式异构计算平台,实现了一种基于该异构计算平台的FPGA动态重配置方法。基于FPGA专用逻辑,设计了使用SWRITE和NREAD事务的DMA数据传输以及使用DOORBELL的消息传递功能,实现了FPGA专用逻辑与主控制处理机间的RapidIO高速互连,为异构计算组件间高速数据传输和FPGA动态重配置技术提供支持。然后,在FPGA逻辑中实现快速傅里叶变换算法并对其进行了动态重配置设计,满足多计算任务对功能与资源的需求。最后,分别对串行RapidIO数据传输性能、加速效率和部分重配置耗时进行了测试,结果表明串行RapidIO传输性能优良、基于FPGA的专用逻辑相对高性能处理器加速效果明显、动态重配置耗时较短,较好满足了任务需求。

Based on the research of heterogeneous computing technology,this paper presents an embedded heterogeneous computing model,and actually builds an embedded heterogeneous computing platform with multiple heterogeneous processors as computing resources interconnected by serial RapidIO high-speed switching bus.An FPGA dynamic reconfiguration method based on the heterogeneous computing platform is also implemented.Based on FPGA-specific logic,DMA data transmission using SWRITE and NREAD transactions and message transfer function using DOORBELL are designed to realize RapidIO high-speed interconnection between FPGA dedicated logic and main control processor.This also supports high-speed data transmission between heterogeneous computing components and FPGA dynamic reconfiguration technology.Then,the fast Fourier transform algorithm is implemented in the FPGA logic and dynamically reconfigured to meet the requirements of functions and resources of multiple computing tasks.Finally,the serial RapidIO data transmission performance,acceleration efficiency and partial reconfiguration time are tested respectively.The results show the serial RapidIO transmission performance is excellent,that the FPGA-based dedicated logic has tremendous advantage over traditional processor on acceleration effect,and that elapsed time of dynamic reconfiguration is short,which wonderfully meets the task requirements.