摘要
雷达在多目标检测中采用有序恒虚警率(OS-CFAR)检测器具有更好的抗干扰能力。本文根据OS-CFAR检测器原理,设计了一种基于FPGA实现方案,利用FPGA面积换取速度的设计思想,采用并行比较的方法,解决了排序耗时长的问题,实现对所有点进行检测,通过仿真验证了设计的正确性。
The radar uses an ordered constant false alarm rate(OS-CFAR)detector for multi-target detection with better anti-interference ability. According to the principle of OS-CFAR detector, this paper designs a design scheme based on FPGA, which uses the design idea of FPGA area exchange speed. It adopts the parallel comparison method to solve the problem of long sorting time, realizes detection of all points, and through simulation. Verifies the correctness of the design.
作者
王瑞
贺鹏飞
刘鹏飞
WANG Rui;HE Peng-fei;LIU Peng-fei(School of Opto-electronic Information Science and Technology, Yantai University, Yantai 264025, China)
出处
《中国集成电路》
2019年第1期39-42,共4页
China lntegrated Circuit
