IBIS Plus模型在DDR I/O抖动分析中的应用

DDR I/O Jitter Analysis with IBIS Plus Model

在高速并联数字接口的设计中,如DDR接口,Simultaneously Switching Noise(SSN)可能会引起系统的噪声或时序裕量的减小,从而影响系统性能,故是一种需要认真分析的现象。在分析中,PISI仿真常用的I/OBuffer Information Specification(IBIS)模型并不能表征SSN导致的抖动,而通常的SSN分析方法是使用I/O的Spice模型进行系统级的仿真,其往往存在仿真时间极长、仿真收敛困难的问题。在本文中,IBISPlus模型被产生和验证,并应用到了对DDR接口的SSN和抖动分析中。结果表明,IBISPlus模型具有仿真精度高、仿真时间短、仿真收敛性好的优点,其为高速数字接口的SSN和抖动分析提供了一种新的高效可靠的的方法。

In the design of high-speed parallel digital interfaces such asDDR Interface, Simultaneously Switching Noise(SSN)is a subject that needs to be paid enough attention to, as it can reduce the voltage or timing margin, anddegrade the performance of the system.I/O Buffer Information Specification(IBIS), the common model for PISI, cannot characterize such jitter induced by SSN. The typical method of considering SSN, performing a system-level spice simulationwith I/O spice models, usually suffers from issues of long running time and bad convergence. In this paper, IBIS Plus was generated and verified, then applied in the SSN and jitter analysis of our DDR interface. It shows that IBIS Plus has the merits of high precision, fast speed, and good convergence in a large-scale simulation. IBIS Plus provides an efficient and accurate method for the SSN and jitter analysis of high-speed digital interfaces.