一种片上集成模拟信号累加结构的CMOS-TDI传感器噪声建模与分析

Noise analysis of a CMOS TDI sensor with on chip signal accumulation in analog domain

提出了一种16级片上模拟累加电路结构以实现时间延迟积分(TDI)功能,累加单元以电荷放大器为基础.为了获得更好的噪声性能,对电路结构的模拟信号链路进行了噪声分析,给出了适用于TDI累加的热噪声模型.分析表明,主要随机热噪声根据累加电路工作的状态不同可以分成电荷传输噪声和直接采样噪声两部分.给出每部分噪声与电路增益大小的关系和相应的抑制方法.采用0. 5μm标准CMOS工艺实现了16×256级CMOS-TDI探测器芯片,流片的测试结果表明16级TDI可以获得11. 22 d B的SNR提升.

This article proposes a 16-stage on-chip analog accumulation circuit architecture to realize time delay integration(TDI).The accumulation unit is based on charge amplifiers.The temporal noise on the analog signal path of the circuit structure is analyzed to enhance the noise performance,and furthermore the model of thermal noise suitable for the TDI process is given.The analysis revealed that the total thermal noise is composed of charge transfer noise and direct sampled noise,according to different stages of accumulators.The relations of each noise component versus circuit gain and corresponding method to suppress it are given.Finally,a 16×256 test chip is taped out under the 0.5μm CIS process,and test results indicate the improvement of 11.22 dB in SNR at the 16 TDI stages.