期刊文献+

基于28 nm工艺数字芯片的时钟树设计 被引量:3

Clock tree synthesis of digital chip based on 28 nm technology
下载PDF
导出
摘要 针对纳米级设计中时钟偏移大、时序不容易收敛等问题,提出了一种有效的时钟树综合(CTS)优化方案。以28 nm工艺的数字芯片为例,根据其时钟结构特点,将CTS过程分成两步完成。利用这种方法,采用Cadence公司的APR工具Encounter对数字模块进行时钟网络的设计;对分步CTS和传统CTS两种方法进行比较。结果表明:使用分步CTS的时钟偏移减小了52%,提高了时钟网络的性能,从而时序得到了很大的改善,芯片泄漏功耗也降低了45%。 An optimized design for clock tree synthesis(CTS)was presented to resolve the large clock skew and timing closure problem of physical design in deep sub-micron technology.Based on a 28 nm digital chip,clock tree synthesis was divided into two steps according to the characteristics of clock structure.What′s more,the APR tool Encounter of Cadence Company was used to design the clock network of digital chip by the optimized method for CTS.The research results showed that the performance of the clock-tree was improved,and the timing was greatly optimized by two-steps CTS.Furthermore,the clock skew was reduced by 52%and the leakage power was reduced by 45%compared with the traditional CTS.
作者 陈力颖 汤勇 吕英杰 CHEN Li-ying;TANG Yong;Lyu Ying-jie(School of Electronics and Information Engineering,Tianjin Polytechnic University,Tianjin 300387,China;Tianjin Key Laboratory of Optoelectronic Detection Technology and Systems,Tianjin Polytechnic University,Tianjin 300387,China;School of Electronic Information and Optical Engineering,Nankai University,Tianjin 300071,China)
出处 《天津工业大学学报》 CAS 北大核心 2019年第1期76-82,共7页 Journal of Tiangong University
基金 天津市应用基础与前沿技术研究计划项目(15JCYBJC16300) 天津科技特派员项目(16JCTPJC45500)
关键词 数字芯片 时钟树设计 数字集成电路 物理设计 时钟树综合 时钟偏移 插入延迟 digital chip clock tree synthesis digital integrated circuits physical design clock skew insertion delay
  • 相关文献

参考文献8

二级参考文献38

  • 1周凤亭,王胤翔,陆生礼.基于Astro的时钟树综合[J].电子器件,2005,28(1):192-195. 被引量:6
  • 2邓博仁,王金城,金西.基于深亚微米下时钟树算法优化的研究[J].半导体技术,2005,30(10):42-45. 被引量:2
  • 3刘祥远,陈书明.高性能VLSI设计中时钟分布网络的问题与解决方法[J].计算机工程与科学,2007,29(6):89-92. 被引量:2
  • 4Cadence. Encounter^TM user guide [M]. USA: Cadence Design Systems Inc. , 2005: 325-350.
  • 5Cadence, Encounter^TM timing closure guide [M]. USA: Cadence Design Systems Inc. , 2006: 25-50.
  • 6Synopsys. Detailed routing parameter docu-mentation [M]. USA: Synopsys, 2007.
  • 7CLEIND.CMOS集成电路版图一概念方法与工具[M].邓红辉,等译.北京:电子工业出版社,2006:1-19.
  • 8REAZ M B I, AMIN N, IBRAHIMY M I, et al. Zero skew clock routing for fast clock tree generation [C] //2008 Canadian Conf Elec Comp Engineer. Niagara Falls, ON, Canada. 2008: 000023-8.
  • 9KURSUNV,FRIEDMANEG.多电压CMOS电路设计[M].马俊婷,等译.北京:机械工业出版社,2008:16-39.
  • 10WANG K, XU Z-W. Synopsys prime power manual release U-2003. 06-QA [M]. New York: McGrawi- Hill Publishers, 2003.

共引文献27

同被引文献4

引证文献3

二级引证文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部