一种改进乘法器的设计与实现

A Design and Implementation of an Improved Multiplier

根据移位相加原理,设计了常见的乘法器,并在此基础上做了两点改进.第一步通过调用条件加法器、条件移位寄存器,以此来减少部分积的加法运算;第二步通过对乘法器的前端处理,进一步减少条件加法器的调用次数,以此来提高运算速度.系统采用模块化设计,分别对三种乘法器进行了实验仿真,仿真结果对比可得:在100 MHz的时钟下,改进的乘法器比常见的乘法器加法器的调用次数少9,运算速度快0. 8 ns,因此在一定程度上验证了改进思想的正确性.

According to the principles of shifter-adder-multiplier,a common multiplier was designed,and on this basis,two improvements had been made.First step,invoking Conditional Adder and Conditional shift Registers to reduce the addition operation of Partial products.Second step,Adding the Front-end processing Module to further reduce the number of calls of Conditional Adder,so as to improve the operation speed.The system used a modular design,and the experimental simulations of three kinds of Multipliers were carried out.The results showed that:Under the 100 MHz clock,the Improved Multiplier invoking Conditional Adder is 9 times less than the Common Multiplier,and the operation speed is faster 0.8ns.Therefore,to a certain extent,it can prove the feasibility of the improvement idea.