小型化铷原子钟高精度频率调节电路设计

A High-Precision Frequency Adjustment Circuit for Miniaturized Rubidium Atomic Clocks

在GPS驯服铷钟等相关应用领域中,小型化铷原子钟的频率调节精度是一项重要性能指标.该性能一般由铷钟整机系统中倍频综合器的数字锁相环(PLL)分辨率决定.目前作者所在的课题组研制了一款小型化高性能铷原子钟,具有良好的稳定度指标,但其频率调节无法满足高精度的需求.针对这一问题,本文对原小型化铷原子钟的倍频综合电路进行了分析研究和改进设计,基于一款高精度直接数字频率合成器(DDS)芯片设计了一种小数倍频综合电路,在保证小型化铷原子钟仍具有高稳定度指标的同时,实现了其高精度频率调节的功能.

Frequency adjusting precision is an important performance indicator of miniaturized rubidium atomic clock(RAC)in some applications,such as the case in GPS disciplined RAC systems.This parameter is determined mainly by the resolution of digital phase-locked loop(PLL)in the frequency multiplier-synthesizer.To improve the frequency adjusting precision of a miniaturized high-performance high-stability RAC developed by our research group,the original RAC circuit scheme was improved by designing and implementing a new decimal frequency multiplier-synthesizer based on a high precision direct digital frequency synthesizer(DDS).Tests showed that this design achieved high precision frequency adjustment,while maintained the frequency stability as high as the original scheme.