应用于级联STATCOM的高精度低成本全FPGA实时仿真模型研究

The Research on Fully FPGA-Based Real-Time Simulation with High Fidelity and Low Cost for the Cascaded STATCOM

针对级联静止无功补偿器(STATCOM),提出一种基于现场可编程门阵列(FPGA)的高精度低成本实时仿真模型。为减小步长,提高仿真精度,提出一种改进开关函数法,将仿真模型分为非线性开关部分和线性电路部分,简化仿真模型,减少仿真计算量。通过计算开关网络外电路电压及比较逻辑得到端口电压,实现H桥死区模式下的仿真,提高模型仿真的精度与实用性。通过实时检测H桥状态,确保二极管单向导电,保证仿真正确性。为了兼顾硬件资源消耗和仿真计算速度,在设计实现上采用串并行结合,以及深度流水线技术。每相12个级联H桥STATCOM实时仿真模型只需一片Cyclone IV EP4CE115即可实现,仿真步长可达到0.85?s。Simulink/PSIM仿真和实际功率电路实验结果均验证了所提出的实时仿真的有效性。

A fully field-programmable-gate-arrays(FPGA)based real-time simulation with high fidelity and low cost for the cascaded static synchronous compensator(STATCOM)is proposed in this paper.To improve the fidelity of the simulation with small time-step,a modified switching-function model is adopted to separate the active switches from the circuit network for computation effort reduction.With the help of external circuit voltage calculation and comparison logic,dead-time period can be covered to improve the precision of model simulation.The real-time detection of the H-bridge state ensures the unidirectional conductivity of diode to achieve the simulation accuracy.To take the hardware resource consumption and simulation step into account,serial and parallel combination design as well as deep pipelining technology is employed for the model implementation.The STATCOM of 12 cascaded H-bridges was implemented on a single FPGA chip of Cyclone IV EP4CE115,and the simulation step can reach 0.85μs.The results of the Simulink/PSIM simulation and real system prototype experiment demonstrate the effectiveness of the proposed real-time simulation.