一种高速Serdes接口测试的ATE设计

ATE Design for High Speed Serdes Interface Test

随着集成电路产业的高速发展,诸如PCI-Express总线、100GBASE以太网、OIF-CEI背板传输等标准串行接口在集成电路上被广泛应用,接口传输速率已经达到16 Gbps～56 Gbps。市场上主流的集成电路自动测试设备,已难以满足这类高速Serdes接口测试需求。因此,为保证Serdes接口的全速测试及高覆盖率的参数级测试,本文设计了一种新的自动化测试系统。其融合了自动测试设备(ATE)与误码测试仪(BERT),实现了高速Serdes接口眼图、抖动、误码率及抖动容限等关键参数的测试,提高了芯片测试覆盖率与结果可信度。

TWith the rapid development of the integrated circuit industry, standard serial interfaces such as PCI-Express bus, 100 GBASE Ethernet, OIF-CEI backplane transmission are widely used in integrated circuits, and the interface transmission rate has reached 16 Gbps to 56 Gbps. The mainstream integrated circuit automatic test equipment in the market is no longer able to meet such high-speed Serdes interface test requirements. Therefore, in order to ensure full speed testing and high coverage parameter level testing of Serdes interface, a new automatic testing system is designed in this paper. With combines automatic test equipment(ATE) and BERT to test key parameters such as eye diagram, jitter, ber and jitter tolerance of high-speed Serdes interface, and improves chip test coverage and result reliability.