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TSV电迁移影响因素的有限元分析 被引量:6

Finite element analysis of factors affecting TSV electromigration
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摘要 本文建立了TSV互连结构三维有限元模型,并对该模型进行了电热耦合分析,分别对比了不同电流密度、环境温度、TSV填充材料等因素对TSV互连结构电迁移失效的影响。结果表明,在一定范围内,电流密度和环境温度是影响TSV互连结构电迁移寿命的主要因素;四种填充物相比,碳纳米管与硅的热膨胀系数更匹配,且产生的焦耳热最小。此外,仿真分析不同TSV长度和孔径对TSV互连结构的温度场分布和焦耳热分布情况的影响。随着TSV长度增大,TSV单位体积热生成率有减小的趋势。电流密度相同情况下,随着TSV孔径增大,产生的焦耳热增加,将加速电迁移现象。 Through the establishment of the three-dimensional finite element model of TSV interconnect structure,the electrothermal coupling method was used to analyze and compare the effects of current density,ambient temperature and TSV filling materials on the electromigration failure of TSV interconnect structure.The results show that,within a certain range,current density and ambient temperature are the main factors affecting the electromigration life of TSV interconnect structures.Compared with the four fillers,the thermal expansion coefficients of carbon nanotubes and silicon are more matched,and the Joule heat generated is the smallest.In addition,the effects of different TSV lengths and apertures on the temperature field distribution and Joule heat distribution of the TSV interconnect structure were investigated.As the TSV aperture increases,the heat generation rate per unit volume of TSV tends to decreases.With the same current density,the Joule heat increases with the increase of TSV aperture,which will accelerate the electromigration phenomenon.
作者 马瑞 苏梅英 刘晓芳 王旭刚 曹立强 MA Rui;SU Meiying;LIU Xiaofang;WANG Xugang;CAO Liqiang(Institute of Microelectronics of Chinese Academy of Sciences,Beijing 100029,China;National Center for Advanced Packaging Co.,Ltd,Wuxi 214135,Jiangsu Province,China)
出处 《电子元件与材料》 CAS CSCD 北大核心 2019年第2期93-97,共5页 Electronic Components And Materials
基金 国家自然科学基金(61474140)
关键词 TSV 电迁移 有限元模拟 电热耦合 TSV electromigration finite element simulation electrothermal coupling
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  • 1封国强,蔡坚,王水弟.硅通孔互连技术的开发与应用[J].电子与封装,2006,6(11):15-18. 被引量:8
  • 2LAU H T. Overview and outlook of through-silicon Via ( TSV ) and 3D integrations [J]. Microelectronics International, 2011, 28 (2): 8-22.
  • 3WU B Q, KUMAR A, PAMARTHY S. High aspect ratio silicon etch: a review [ J]. Journal of Applied Physics, 2010, 108 (5): 1101-1120.
  • 4HONG S C, LEE W G, KIM W J, et al. Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking [J]. Microelectronics Reliability, 2011, 51 (12): 2228-2235.
  • 5LAU J H, SOON W H, KUMAR A, et al. Fabrication of high aspect ratio TSV and assembly with fine-pitch low- cost solder microbump for Si interposer technology with high-density interconnects [J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2011, 1 (9): 1336-1344.
  • 6RANGANATHAN N, PRASAD K, BALASUBRAMANIAN N, et al. A study of thermo-mechanical stress and its impact on through-silicon vias [ J ]. Journal of Micromechanics and Microengineering, 2008, 18 ( 7 ) : 5018 - 5030.
  • 7FENG X, CAO I-I Y, YU H, et al. Study of internal stress on electroplating copper used in through silicon via filling [C] //// Proceedings of the 2011 InternationalConference on Electronic Packaging Technology and High Density Packaging. Shanghai, China, 2011: 1018- 1021.
  • 8KWON W S, ALASTAIR T D, TEO K H, et al. Stress evolution in surrounding silicon of Cu-filled through- silicon via undergoing thermal annealing by multi- wavelength micro-Raman spectroscopy [ J]. Applied Physics Letters, 2011, 98 (23): 232106-232108.
  • 9TRIGG A D, YU L H, CHENG C K, et al. Three dimensional stress mapping of silicon surrounded by copper filled through silicon vias using polychromator- based multi-wavelength micro raman spectroscopy [ J]. Applied Physics Express, 2010, 3 (8) : 086601 - 086603.
  • 10THOMPSON S E, SUN G, CHOI Y S, et al. Uniaxial- process-induced strained-Si: extending the CMOS roadmap [ J]. IEEE Transactions on Electronic Devices, 2006, 53 (5): 1010-1020.

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