期刊文献+

基于低功耗SoC的微型图像采集系统设计 被引量:6

Design of Miniature Image Acquisition System Based on Low Power System on Chip
下载PDF
导出
摘要 针对低成本和低功耗的物联网SoC芯片发展要求,基于SMIC 55 nm CMOS工艺,以低功耗开源处理器RI5CY的SoC芯片为平台,结合片内含有DSP与A/D转换功能的低电压CMOS图像传感器OV7725,设计并实现了一款基于开源RISC_V指令集架构SoC芯片的图像采集控制系统.文中介绍了图像采集控制系统的结构,并详细阐述基于AHB总线的图像采集控制器的设计.控制器采用一种改进的异步FIFO来实现不同时钟域的同步设计,具有小面积和低功耗的特点.通过Modelsim仿真、DC综合以及FPGA验证,结果表明:该系统实现了视频图像数据的采集和传输,操作流程简单,易于软件调试,支持应用最高带宽可达37 MB/s. SoC芯片系统的时钟主频为200 MHz,芯片总面积为3 250×3 648μm2,总功耗仅为24.419 mW. Based on the development requirements of low-cost and low-power Internet SoC chip, an image acquisition and control system is designed and implemented based on open source RISC_V instruction set architecture SoC chip and SMIC 55nm CMOS process, which uses the low-power open source processor RI5CY SoC chip as a platform and combined with the Low-Voltage CMOS Image Sensor OV7725 with the integrated DSP and A/D conversion chip inside. This paper introduces the block diagram of the image acquisition and control system, and describes a design of image acquisition controller based on AHB bus in detail. An improved asynchronous FIFO with low power and small area is used to realize the synchronous design of different clock domains. According to the results of Modelsim simulation, DC synthesis and FPGA verification shows that the system realizes the video image data acquisition and transmission,which operation flow is simple and easy to debug, and the maximum of the data transmission bandwidth come up to 37MB/s. The chip total area is 3250 μm x 3648 μm and power consumption is only 24.419 mW.
作者 胡锦 谢立红 邹望辉 张磊 胡啸东 HU Jin;XIE Lihong;ZOU Wanghui;ZHANG Lei;HU Xiaodong(School of Physics and Electronics,Hunan University,Changsha 410082,China;Institute of Computing Technology of Chinese Academy of Sciences,Beijing 100080,China;Netforward Shenzhen,Shenzhen 518057,China)
出处 《湖南大学学报(自然科学版)》 EI CAS CSCD 北大核心 2019年第2期86-91,共6页 Journal of Hunan University:Natural Sciences
基金 国家自然科学基金资助项目(61674055)~~
关键词 图像采集 SOC RISC_V 异步FIFO image acquisition Soc RISC_V asynchronous FIFO
  • 相关文献

参考文献3

二级参考文献22

  • 1芦跃峰,姜昌金.网络化视频监控系统的研究与实现[J].制造业自动化,2004,26(8):10-12. 被引量:3
  • 2张红南,刘晓巍,邓蓉,张卫青,胡锦,赵欢.IC卡的优化设计及FPGA仿真[J].湖南大学学报(自然科学版),2006,33(2):66-69. 被引量:2
  • 3BOLCHINI C,QUARTA D.SEU mitigation for sram-based fpgas through dynamic partial reconfiguration[C]//Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI.Italy:ACM Press,2007:55-60.
  • 4STERPONE L.Analysis of the robustness of the TMR architecture in SRAM-based FPGAs[J].IEEE Transaction on Nuclear Science,2005,52(5):1545-1549.
  • 5TESSIER R,BETZ V.Power-efficient RAM mapping algorithms for FPGA Embedded memory blocks[J].IEEE Trans.of Computer-Aided Design,2007,26(2):278-289.
  • 6FRIGERIO L,SALICE F.Ram-based fault tolerant state machines for FPGA[C]//Proceedings of IEEE Design and Fault Tolerant Symposium,Rome,Italy:IEEE Press,2007,312-320.
  • 7GYORFI T,CRE O.High performance true random number generator based on FPGA block RAMs[C] //Proceedings of the 2009 IEEE International Symposium on Parallel and Distributed Processing Rome,Italy:IEEE Press,2009:1-8.
  • 8MAESTROo J A,REVIRIEGO P.Study of the effects of MBUs on the reliability of a 150 nm SRAM device[C]//Proceedings of the 45th annual Design Automation Conference.New York:ACM Press,2008:930-935.
  • 9MAESTRO J A,REVIRIEGO P.Reliability of single-error correction protected memories[J].IEEE Transactions on Reliability,2009,58(1):193-201.
  • 10ARGYRIDES C,VARGAS F.Embedding current monitoring in h-tree RAM architecture for multiple SEU tolerance and reliability improvement[C] // Proceedings of the 2008 14th IEEE International On-Line Testing Symposium,Washington:IEEE Press,2008,155-160.

共引文献9

同被引文献40

引证文献6

二级引证文献16

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部