基于FPGA的极化码半平行CA-SCL译码器设计

Implement of the CA-SCL Semi-parallel Decoding Algorithm Based on FPGA

极化码(Polar Codes,PC)是一种在理论上能达到香农极限的纠错编码技术,其受到广泛学者的研究。传统的连续删除(Successive Cancelation,SC)译码算法在有限的情况下性能较差,学者对其优化,提出了公认具有较好性能的CA-SCL算法。为了该算法在硬件实现中取得译码性能与硬件译码复杂度的平衡,使用Quartus II设计了基于FPGA的半平行CA-SCL极化码译码器,此设计实现了较小的硬件资源占用率及较高的吞吐率。最后使用Matlab从量化与未量化来验证该算法优异的译码器性能。设计码长为1024,码率为1/2,列表宽度L=32的极化码CA-SCL译码算法。译码器在150MHz的工作频率下的吞吐率可达到25.6Mbps,资源占用率仅为7%。

Polar codes (PC) is a kind of error-correction codes,which can theoretically reach the Shannon limit. It has been widely studied by scholars. The traditional Successive Cancellation (SC) decoding algorithm has poor performance under limited conditions. Scholars have optimized it and put forward the CA-SCL algorithm which have been recognized as having better performance. In order to obtain the balance between the decoding performance and the hardware decoding complexity in the hardware implementation, a polar code decoder of semi-parallel structure basing on FPGA has been designed using Quartus II. This design achieves a smaller hardware resource occupation rates and higher throughput rates. Finally, Matlab can be used to verify the excellent decoder performance of the algorithm from quantization and un-quantization. The design is synthesized for a block length of N=1024 bits, code rate 1/2 and list size L=32. When the clock frequency is 150MHz, the decoding throughput can be up to 25.60Mbps, and the resource occupancy rate is only 7%.