基于0.18μm工艺的I/O端口ESD防护设计

Design of I/O Port ESD Protection Based on 0.18 μm Process

当两个拥有不同电势的物体接触时,电势差会导致电荷流动,从而产生放电,这种现象称为静电放电(Electrostatic Discharge,ESD)。ESD所产生的瞬间高电压和大电流,会烧毁击穿半导体中的器件,最终导致整个半导体芯片永久性失效。随着硅基CMOS工艺技术的不断进步,由ESD引起的失效问题也随着特征尺寸的变小而日益严重。首先分析了几种常见的静电放电模式以及测试模型,随后基于SMIC公司0.18μm BCD工艺,在传统GGNMOS抗辐照ESD结构基础上进行优化,设计一款GGNMOS+RC Power Clamp抗ESD结构。经流片测试后,证明该款电路抗ESD能力强,且性能稳定。

ESD ( Electrostatic Discharge, ESD ) refers to the limited charge transfer between two objects of different potential, thus caused by the Discharge phenomenon. The instantaneous high voltage and current generated by ESD will burn the devices in the semiconductor and eventually lead to the permanent failure of the entire semiconductor chip. With the continuous progress of silicon based CMOS technology, the failure problem caused by ESD is becoming more and more serious with the reduction of characteristic size. This paper analyzes several common electrostatic discharge modes and test models, then optimizes a GGNMOS+RC Power Clamp anti-esd structure on the basis of the traditional GGNMOS anti-radiation ESD structure based on the 0.18 μm BCD process of SMIC. It is proved that this circuit has strong ESD resistance capability and stable performance after the flow test.