基于FPGA+SCV64架构的VME总线从模块开发

Development of VME Bus Slave Module Based on FPGA+SCV64 Architecture

为满足新机VME总线模块电路板深修的需要,基于VME总线接口协议芯片SCV64,开发了具有接收VME总线信号读写操作功能的从模块。该从模块可实现对机上VME总线模块通信能力检测。给出其硬件架构与各部分电路设计,基于Verilog语言对其读写功能进行软件开发,并给出其硬件设计与软件开发过程中需要注意的问题。对从模块功能进行测试,测试结果表明其功能有效。研制的VME总线从模块能够为后续VME总线模块的测试与维修提供技术支撑。

In order to meet the needs of the deep repair of the VME bus module circuit board on the new aircraft,based on the VME bus interface protocol chip SCV64,a slave module that accepts the VME bus signal read/write operation function has been developed.The slave module can detect the communication capability of the on-board VME bus module.The hardware architecture and various circuit designs are given.The software is developed based on Verilog HDL.The issues that need to be addressed during the hardware design and software development process are described.The slave module was tested and the results showed that its function was available.The developed VME bus slave module can provide technical support for testing and repairing VME bus modules in subsequent new models.