基于极性发射机的两点调制锁相环的设计

Design of Two-point Modulation Phase-locked Loop for Polar Transmitter

采用0.11μm 1P6M CMOS工艺设计与研究了一款适用于蓝牙极性调制发射机的两点调制锁相环.为了校正锁相环中两个相位调制路径的环路增益,降低采用该锁相环的发射机的频移键控误差,提出了一种新型的增益校正方法,并基于该方法设计了低相位噪声、低锁定时间的两点调制锁相环电路.芯片的测试结果表明,当压控振荡器震荡在4.8 GHz时,该锁相环在偏离4.8 GHz 10 kHz、1 MHz和3 MHz时的相位噪声依次为-83、-108和-114 dBc/Hz,采用该锁相环的极性调制发射机发射0 dBm信号时频移键控误差为2.97%,该锁相环的芯片面积为0.32 mm^2,整体性能满足蓝牙射频芯片测试规范要求.

Two-point modulation phase-locked loop(PLL)for Bluetooth polar transmitter was studied and designed by using 0.11μm 1P6M CMOS process.In order to correct the loop gain of two phase modulation paths in the PLL and reduce the frequency shift keying error of using the phase-locked loop,a new gain correction method was proposed.And a new phase-locked loop circuit of two-point modulation based on gain calibration was proposed to reduce phase noise of PLL and accelerate the locking time of phase-locked loop.Chip measured results show that when voltage controlled oscillator oscillates at 4.8 GHz,the phase noises at 10 kHz,1 MHz,3 MHz offsets are-83 dBc/Hz,-108 dBc/Hz and-114 dBc/Hz,respectively.When using the polar transmitter of phase-locked loop to transmit the 0 dBm signal,the FSK error is 2.97%,and the phase-locked loop occupies 0.32 mm 2.The overall performance meets the requirements of Bluetooth RF chip test specification.