基于FPGA的DES算法硬件实现

Hardware Implementation of DES Algorithm Based on FPGA

加密算法是军用通信研究的重点之一,信息加密的优劣决定了通信的安全性。DES算法(Data Encryption Standard)是一种具有极高安全性且广泛应用于数据加密领域的加密标准,其常常应用于POS,ATM,IC卡等中。将DES算法与现代军用武器相结合,可以大幅度提高大型武器的可靠性。根据DES算法的基本原理,从减少资源占用量的角度出发,使用VHDL语言在FPGA平台上进行代码设计和逻辑实现;较小逻辑资源、更高的时钟频率更加适用于军用双向通信链路系统。

Encryption algorithm is one of the focuses of military communication research.The quality of information encryption determines the security of communication.The DES algorithm(Data Encryption Standard)is an encryption standard that is extremely secure and widely used in the field of data encryption.It is often used in POS,ATM,IC cards,and the like.Combining the DES algorithm with modern military weapons can greatly improve the reliability of large weapons.According to the basic principle of DES algorithm,from the perspective of reducing resource consumption,VHDL language is used for code design and logic implementation on FPGA platform;smaller logic resources and higher clock frequency are more suitable for military two-way communication link system.