基于码密度的高精度时间数字转换器设计

Design of High-Precision TDC based on Code Density

采用基于码密度的技术实现了一种基于FPGA xilinx7系列芯片的高精度时间数字转换器(TDC)系统,包括精密时间测量模块、数据校准系统、粗测量模块以及逻辑控制模块。设计该系统的关键部分在于底层硬件(FPGA)资源中存在的大量延时单元,并且该系统要求延时单元有一定的稳定性。利用FPGA芯片底层自带的CARRY4模块,构造了由64个快速进位链(CARRY4)组成的延迟链系统。此外,利用码密度的优点,解决特殊进位链延时单元带来的非线性问题。该方法可以有效地消除由于布局布线所带来的实际误差。通过实验表明,利用该方法可以准确地反映延迟单元在实际中运用中的时间分布,降低积分非线性和微分非线性。

A high precision time digital converter (TDC) system based on FPGA xilinx7 series chip is designed by using code density-based technology, including precision time measurement module, data calibration system, rough measurement module and logic control module. The key part in designing this system is that there exist a large number of delay units in the underlying hardware (FPGA) resources, and the delay units are required to have certain stability. A delay chain system consisting of 64 fast carry chains (CARRY4) is constructed by using CARRY4 module at the bottom of FPGA chip. In addition, by making use of the advantage of code density, the nonlinear problem caused by special carry chain delay unit is solved. This method can effectively eliminate the actual errors caused by the layout and wiring, and reduce the integral nonlinearity and the differential nonlinearity. Experimental results indicate that the proposed method can accurately reflect the time distribution of delay units in practice.