期刊文献+

500V增强型与耗尽型集成VDMOS器件设计 被引量:1

Design of 500 V Enhancement and Depletion Integrated VDMOS Devices
下载PDF
导出
摘要 增强型与耗尽型集成VDMOS器件是LED驱动电路中一种高效、低成本的功率器件。其设计制造要解决的主要问题是两种VDMOS器件工艺的集成问题和两种器件之间的隔离问题。提出一种隔离良好、芯片面积较小的增强型与耗尽型集成VDMOS设计和制造方法,耗尽管位于增强管里面比耗尽管位于增强管外面时耗尽管芯片面积减小74%。测试结果表明500 V增强型VDMOS击穿电压BVDSS平均值为550 V,耗尽型VDMOS击穿电压BVDSX平均值为540 V,增强型VDMOS平均阈值电压VTH为3.2 V,耗尽型VDMOS平均阈值电压VP为-3.7 V,两种管子总良率在94%以上,达到预期的设计目的,并成功应用于LED等产品中。 Enhancement and depletion integrated VDMOS devices are efficient and low-cost power devices for LED drive circuits. The main problems to be solved in the design and fabrication are the integration of two kinds of VDMOS processes and the isolation between the two devices. Methods of design and manufacture are provided for enhancement and depletion integrated VDMOS devices to get excellent isolation and small chip area in this paper. The area of the depletion mode VDMOS device decreases by 74% when it lies inside the enhancement mode tube compared with lying outside the enhancement mode tube. Test results show that average breakdown voltage BVDSSof enhancement mode tube is 550 V and average breakdown voltage BVDSXof depletion mode tube is 540 V. Average threshold voltage VTHof enhancement mode VDMOS is 3.2 V, and that of depletion mode VDMOS is-3.7 V. The total yield was above 94%. The design has achieved the desired purpose, and the devices have been successfully applied to LED products.
作者 李学会 黄昌民 詹小勇 许玉欢 LI Xuehui;HUANG Changmin;ZHAN Xiaoyong;XU Yuhuan(Wuxi Changde Microelectronic Co., Ltd., Wuxi 214028, China)
出处 《电子与封装》 2019年第4期36-40,共5页 Electronics & Packaging
关键词 增强型VDMOS 耗尽型VDMOS 元胞结构 隔离结构 工艺设计 enhancement mode VDMOS depletion mode VDMOS cellular structure isolation structure process design
  • 相关文献

参考文献2

二级参考文献15

  • 1卢豫曾.高压RESURF LDMOSFET的实现[J].电子学报,1995,23(8):10-14. 被引量:6
  • 2陈星弼.功率MOSFET和高压集成电路[M].南京:东南大学出版社,1990..
  • 3TEMPLE V. Increasing avalanche breakdown voltage and controlled surface electric field using a junction termination extension technique [J]. IEEE Trans Elec Dev, 1983, 30(8): 954-957.
  • 4STEFANOY E, CHARITAT G. Design methodology and simulation tool for floating ring termination [J]. Sol Sta Elec, 1998, 42(12) : 2251-2257.
  • 5SOUZA M. A novel area efficient floating field limit ring edge termination technique [J]. Sol Sta Elec, 2000, 44(8).. 1381-1386.
  • 6HE J, CHAN M, ZHANG X, et al. A new analytic method to &,sign multiple floating field limiting rings of power devicc.s [J]. Sol Sta Elec, 2006, 50(8): 1375-1381.
  • 7LIAO C N. Potential and electric field distribution analysis of field limiting ring and field plate by device simulator [C] // IEEE Conf Power Elec Drive Syst. Bangkok. 2007: 451-455.
  • 8PADMANABHAN V, RHINEHART R. A novel termination criterion for optimization [C] // Americ Control Conf Proc. Portland, OR, USA. 2005.. 2281- 2286.
  • 9KIM Y H, LEE H S. A new edge termination technique to improve voltage blocking capability and reliability of field limiting ring for power devices [C] //IEEE Int Conf Integr Circ Des Technol. Austin, TX, USA. 2008. 71-74.
  • 10SUBHAS J V. A novel metal field plate edge termination for power devices [J]. Microelec J, 2001, 32(4) : 323-326.

共引文献12

同被引文献2

引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部