摘要
本文采用HLMC 55nm工艺,设计了一款高速逐次逼近型模数转换器。为了提高模数转换器的转换速度,在设计中采用了特殊的电容阵列布局方式,减小高位电容降低电容DAC对建立时间和建立精度的要求;采用快复位式比较器减小比较器的比较延迟;采用编程可控的环路延迟,控制环路建立的精度和速度。在80MHz输入采样时钟的频率下,测试得到的有效位数超过8.2bit。
A high-speed Successive Approximation Register Analog to Digital Converter is designed with HLMC 55nm technology.To meet settling and resolution requirements,special arrangement of capacitor array,small capacitor unit and fast-reset comparator are adopted in this work.Meanwhile a programmable delay control block is inserted in feedback loop to improve the settling of MSB.With 80MHz sampling rate,the measured enob is 8.2bits.
作者
赵喆
栾昌海
刘寅
ZHAO Zhe;LUAN Chang-hai;LIU Yin(Beijing Huada Empyrean Software Co.,Ltd.)
出处
《中国集成电路》
2019年第4期32-37,共6页
China lntegrated Circuit
关键词
异步采样
逐次逼近
高速比较器
模数转换器
Asynchronous Sampling
Successive Approximation
High Speed Comparator
Analog to Digital Converter
