可重构阵列处理器Harris算法并行化实现

Reconfigurable Array Processor Harris Algorithm is Implemented in Parallel

本文提出可重构阵列处理器Harris并行化的算法映射方式,其中可重构阵列处理器解决了算法在硬件上修改就需要结构重新调整的缺陷同时簇间并行化解决了算法在软件速度和延时的缺陷.通过modelsim、Xilinx公司硬件设计工具ISE和BEE4开发平台实现Harris算法对分辨率为512*512的图像映射,实验结果表明,整个算法映射时间为0.143 ms,这个时间相比于相同条件下CPU、GPU、FPGA实现Harris算法映射的时间都短.

In this paper, the reconfigurable array processor Harris parallelization algorithm mapping methods, the reconfigurable array processor solves the algorithm on the hardware modification requires the defect of structure readjustment between cluster parallel at the same time solve the defect of the algorithm in software speed and time delay.By modelsim, Xilinx ISE company hardware design tools and BEE4 development platform to realize the Harris algorithm to the resolution of 512 * 512 image map, the experiment results show that the algorithm mapping time of 0.143 ms, under the condition of the time compared to the same CPU, GPU, the FPGA implementation Harris algorithm mapping time is short.